In semiconductor devices, interconnects (e.g., lines, vias) are typically formed using a damascene process in which a metal layer (e.g., copper, tungsten, etc.) is deposited in an opening etched into one or more dielectric layers on a substrate. Several chemical mechanical polishing (CMP) steps are performed during the damascene process. One such CMP step is used to remove a barrier layer and to planarize the metal layer and a top dielectric layer until the metal layer becomes coplanar with the top dielectric layer. This CMP step is typically performed for a fixed time, which often results in a high variability from wafer to wafer in the resistance of the metal interconnects that are formed.